#

verilog-components

Here are 27 public repositories matching this topic...

ultraembedded / cores

Various HDL (Verilog) IP Cores

audio asic fpga usb rtl verilog spi sram uart verilog-hdl verilog-components verilator i2s sdram

Updated Jul 1, 2021
Verilog

ZipCPU / dblclockfft

A configurable C++ generator of pipelined Verilog FFT cores

fpga gplv3 verilog fft verilog-components verilator

Updated Apr 18, 2024
C++

ZipCPU / sdspi

SD-Card controller, using either SPI, SDIO, or eMMC interfaces

spi-interface fpga verilog sd-card sdio wishbone verilog-components verilator axi emmc wishbone-bus sd-interface

Updated Nov 27, 2024
Verilog

TimRudy / ice-chips-verilog

IceChips is a library of all common discrete logic devices in Verilog

fpga open-hardware eda digital-logic icestorm iverilog logic-circuit verilog-components 7400

Updated Nov 20, 2024
Verilog

neelkshah / MIPS-Processor

5-stage pipelined 32-bit MIPS microprocessor in Verilog

verilog microprocessor computer-architecture microprocessors verilog-hdl mips-architecture mips-processor bits-pilani computer-organization verilog-components verilog-snippets mips-instructions computer-organisation verilog-programs verilog-simulator verilog-project

Updated Apr 3, 2020
Verilog

spam-1

Johnlon / spam-1

Home Brew 8 Bit CPU Hardware Implementation including a Verilog simulation, an assembler, a "C" Compiler and this repo also contains my research and learning. See also the Hackaday.IO project. https://hackaday.io/project/166922-spam-1-8-bit-cpu

design cpu vhdl assembler verilog rom ttl alu 8bit cmos verilog-components logism homebrew-cpu

Updated Aug 27, 2023
Verilog

adibis / Interrupt_Controller

An 8 input interrupt controller written in Verilog.

verilog hdl verilog-components verilog-project

Updated Mar 22, 2012
Verilog

TimRudy / uart-verilog

A simple 8 bit UART implementation in Verilog, with tests and timing diagrams

fpga open-hardware eda digital-logic hardware-designs serialport icestorm uart-verilog iverilog verilog-components uart-interface

Updated May 28, 2023
Verilog

wyvernSemi / mem_model

High speed C/C++ based behavioural VHDL/Verilog co-simulation memory model

simulation vhdl verilog questasim ghdl avalon memory-model test-bench pli verilog-components verilator axi nvc dpi-c cosimulation vivado-simulator verilog-testbenches

Updated Nov 20, 2024
VHDL

ZipCPU / wbfmtx

A wishbone controlled FM transmitter hack

fpga hack verilog wishbone verilog-components wishbone-bus fm-transmitter

Updated Jan 16, 2024
Verilog

Wissance / QuickSPI

Two Verilog SPI module implementations (hard and soft) with advanced options and AXI Full Interface

Updated Nov 21, 2017
Verilog

BrianHGinc / Verilog-Floating-Point-Clock-Divider

Provide / define the INPUT_CLK_HZ parameter and the BHG_FP_clk_divider.v will generate a clock at the specified CLK_OUT_HZ parameter using fractional floating point division.

verilog verilog-hdl verilog-components clock-generator

Updated Aug 11, 2022
Verilog

emrealci / FPGA-Verilog

Practices related to the fundamental level of the programming language Verilog.

fpga verilog hardware-designs hdl multiplexer comparator xilinx-fpga verilog-components latch verilog-project frequency-divider sr-latch

Updated Jan 16, 2023
Verilog

EhsanShahbazii / Digital-VLSI-System-Design-Projects

سورس کد پروژه های درس طراحی سیستم های دیجیتال برنامه پذیر دانشگاه تبریز مقطع کارشناسی رشته مهندسی کامپیوتر

verilog vlsi verilog-components verilog-project verilog-code

Updated Jan 9, 2024
Verilog

IzyaSoft / EasyHDLLib

A coocbook of HDL (primarily Verilog) modules

fpga verilog altera fifo hdl verilog-hdl xilinx-fpga frequencies frequency-analysis verilog-components verilog-library verilog-snippets clock-divider

Updated Apr 24, 2017
Verilog

University-projects

trojanink / University-projects

Some of the projects I developed during my studies at University of Thessaly, Electrical & Computer Engineering Dpt.

c university assembly homework projects verilog assembly-language assembly-language-programming studies c-language verilog-components verilog-project verilog-code c-language-math computer-engineering-dpt

Updated Aug 6, 2020
C

ferhatozkan / Digital-Logic-Design-Project

University of Marmara, CSE3015 2018 Fall Project

java cpu assembly assembler verilog logisim verilog-components logic-design

Updated May 14, 2019
Java

yvesemmanuel / introduction_verilog

digital systems

verilog digital-systems verilog-components verilog-project

Updated Aug 26, 2021
Verilog

yvesemmanuel / microwave

second project - Digital System

verilog digital-systems verilog-components verilog-project

Updated Sep 7, 2021
Verilog

klsavaj / VerilogCode-All-Modules-COA-Notes

modules computer-architecture verilog-components

Updated May 29, 2021
HTML

Improve this page

Add a description, image, and links to the verilog-components topic page so that developers can more easily learn about it.

Curate this topic

Add this topic to your repo

To associate your repository with the verilog-components topic, visit your repo's landing page and select "manage topics."