Sam

.gitignore

@@ -21,3 +21,16 @@ __pycache__
 # This is generated by Questa tool when running DV simulations
 modelsim.ini
 
+vendor/riscv.tar.gz
+vendor/verilator/
+install/
+sim.fst
+
+*.tar.gz
+logs*/
+*.log
+*.csv
+*.old*
+*.map
+*.vc
+synth/

Makefile.tools

@@ -0,0 +1,69 @@
+prj_path := $(shell git rev-parse --show-toplevel)
+num_cores := $(shell nproc)
+num_cores_half := $(shell echo "$$(($(num_cores) / 2))")
+CXX := g++-10
+
+
+INSTALL_PREFIX          ?= install
+INSTALL_DIR             ?= $(prj_path)/${INSTALL_PREFIX}
+GCC_INSTALL_DIR         ?= ${INSTALL_DIR}/riscv-gcc
+LLVM_INSTALL_DIR        ?= ${INSTALL_DIR}/riscv-llvm
+ISA_SIM_INSTALL_DIR     ?= ${INSTALL_DIR}/riscv-isa-sim
+ISA_SIM_MOD_INSTALL_DIR ?= ${INSTALL_DIR}/riscv-isa-sim-mod
+VERIL_SRC_ROOT           ?= $(prj_path)/vendor
+VERIL_INSTALL_DIR       ?= ${INSTALL_DIR}/verilator
+VERIL_VERSION           ?= v5.028
+
+all: verilator riscv32-gcc riscv32-llvm dev-dep
+# Verilator
+verilator: ${VERIL_INSTALL_DIR}/bin/verilator
+
+${VERIL_INSTALL_DIR}/bin/verilator:
+	rm -fr $(VERIL_SRC_ROOT)/verilator
+	cd $(VERIL_SRC_ROOT) && git clone https://github.com/verilator/verilator.git
+	# Checkout the right version
+	cd $(VERIL_SRC_ROOT)/verilator  && git reset --hard && git fetch && git checkout ${VERIL_VERSION}
+	# Compile verilator
+	cd $(VERIL_SRC_ROOT)/verilator  && git clean -xfdf && autoconf && \
+	./configure --prefix=$(VERIL_INSTALL_DIR) CXX=g++-10  && make -j$(num_cores_half)  && make install
+	touch ${VERIL_INSTALL_DIR}/bin/verilator
+
+cores:
+	@num_cores=$$(nproc); \
+	num_cores=$$((num_cores / 2)); \
+	echo "Number of cores available on this machine (divided by 2): $$num_cores"
+
+riscv32-gcc: $(GCC_INSTALL_DIR)
+
+vendor/riscv32-elf-gcc.tar.gz: vendor/riscv32-elf-gcc.url
+	cd vendor && \
+	wget `cat $(CURDIR)/$<` -O riscv32-elf-gcc.tar.gz && \
+	touch riscv32-elf-gcc.tar.gz
+
+$(GCC_INSTALL_DIR): vendor/riscv32-elf-gcc.tar.gz
+	rm -fr $(GCC_INSTALL_DIR)
+	mkdir -p $(INSTALL_DIR)
+	cd vendor && \
+	tar -xzvf riscv32-elf-gcc.tar.gz -C  $(INSTALL_DIR)/ riscv	
+	mv $(INSTALL_DIR)/riscv $(GCC_INSTALL_DIR)
+	touch  $(GCC_INSTALL_DIR)
+
+riscv32-llvm: $(LLVM_INSTALL_DIR)
+
+vendor/riscv32-elf-llvm.tar.gz: vendor/riscv32-elf-llvm.url
+	cd vendor && \
+	wget `cat $(CURDIR)/$<` -O riscv32-elf-llvm.tar.gz && \
+	touch riscv32-elf-llvm.tar.gz
+
+$(LLVM_INSTALL_DIR): vendor/riscv32-elf-llvm.tar.gz
+	rm -fr $(LLVM_INSTALL_DIR)
+	mkdir -p $(INSTALL_DIR)
+	cd vendor && \
+	tar -xzvf riscv32-elf-llvm.tar.gz -C  $(INSTALL_DIR)/ riscv	
+	mv $(INSTALL_DIR)/riscv $(LLVM_INSTALL_DIR)
+	touch  $(LLVM_INSTALL_DIR)
+
+dev-dep:
+	sudo apt-get install libelf-dev -y
+	sudo apt-get install srecord -y
+

README.md

@@ -3,6 +3,51 @@
   <img src="https://ibex.reports.lowrisc.org/opentitan/latest/summary.svg">
 </a>
 
+# ISOLDE
+First time:   
+```sh
+. ./setup.sh 
+```
+* install toolchain
+
+```sh
+make -f Makefile.tools
+```
+otherwise:  
+```sh
+. ./eth.sh 
+```
+see also [isolde/simple_system/README.md](isolde/simple_system/README.md)
+## Run hello-world
+```sh
+fusesoc --cores-root=. run --target=sim --setup --build  lowrisc:ibex:ibex_simple_system $(util/ibex_config.py small fusesoc_opts)
+make -C examples/sw/simple_system/hello_test
+./build/lowrisc_ibex_ibex_simple_system_0/sim-verilator/Vibex_simple_system -t --meminit=ram,./examples/sw/simple_system/hello_test/hello_test.elf
+```
+Result
+```
+Tracing enabled.
+Writing simulation traces to sim.fst
+TOP.ibex_simple_system.u_top.u_ibex_tracer.unnamedblk2.unnamedblk3: Writing execution trace to trace_core_00000000.log
+Terminating simulation by software request.
+- ../src/lowrisc_ibex_sim_shared_0/./rtl/sim/simulator_ctrl.sv:93: Verilog $finish
+Received $finish() from Verilog, shutting down simulation.
+
+Simulation statistics
+=====================
+Executed cycles:  13144
+Wallclock time:   0.048 s
+Simulation speed: 273833 cycles/s (273.833 kHz)
+Trace file size:  517730 B
+
+You can view the simulation traces by calling
+$ gtkwave sim.fst
+
+Performance Counters
+====================
+Cycles:               476
+Instructions Retired: 261
+```
 # Ibex RISC-V Core
 
 Ibex is a production-quality open source 32-bit RISC-V CPU core written in

eth.sh

@@ -0,0 +1,30 @@
+#!/usr/bin/env bash
+# Copyleft
+
+# Define environment variables
+MINICONDA=~/miniconda3/etc/profile.d/conda.sh
+MINICONDA_ENV=ibex
+# To activate this environment, use
+#
+#     $ conda activate ibex
+#
+# To deactivate an active environment, use
+#
+#     $ conda deactivate
+
+# Get the root directory of the Git repository
+export ROOT_DIR=$(git rev-parse --show-toplevel)
+
+export BENDER=~/eth/bin/bender
+export PULP_RISCV_GCC_TOOLCHAIN=$ROOT_DIR/install/riscv
+export GCC_TOOLCHAIN=$ROOT_DIR/install/riscv-gcc/bin
+export LLVM_TOOLCHAIN=$ROOT_DIR/install/riscv-llvm/bin
+export CC=gcc-10
+export CXX=g++-10
+
+
+source $MINICONDA
+conda activate $MINICONDA_ENV
+
+export PATH=~/eth/bin:~/verible/bin:$ROOT_DIR/install/verilator/bin:$GCC_TOOLCHAIN:$PATH
+source ~/vivado.sh

examples/sw/.gitignore

@@ -4,3 +4,4 @@
 *.elf
 *.vmem
 *.d
+*.headers

examples/sw/simple_system/common/common.mk

@@ -8,7 +8,7 @@ COMMON_SRCS = $(wildcard $(COMMON_DIR)/*.c)
 INCS := -I$(COMMON_DIR)
 
 # ARCH = rv32im # to disable compressed instructions
-ARCH ?= rv32imc
+ARCH ?= rv32imc_zicsr
 
 ifdef PROGRAM
 PROGRAM_C := $(PROGRAM).c
@@ -44,6 +44,8 @@ all: $(OUTFILES)
 ifdef PROGRAM
 $(PROGRAM).elf: $(OBJS) $(LINKER_SCRIPT)
 	$(CC) $(CFLAGS) -T $(LINKER_SCRIPT) $(OBJS) -o $@ $(LIBS)
+	$(OBJDUMP) -dh  $@ >[email protected]
+
 
 .PHONY: disassemble
 disassemble: $(PROGRAM).dis

ibex_configs.yaml

@@ -192,3 +192,24 @@ experimental-branch-predictor:
   MHPMCounterNum           : 0
   MHPMCounterWidth         : 40
 
+# ===============================
+# * ISOLDE *
+# ===============================
+isolde:
+  RV32E                    : 0
+  RV32M                    : "ibex_pkg::RV32MSingleCycle"
+  RV32B                    : "ibex_pkg::RV32BNone"
+  RegFile                  : "ibex_pkg::RegFileFF"
+  BranchTargetALU          : 0
+  WritebackStage           : 0
+  ICache                   : 1
+  ICacheECC                : 0
+  ICacheScramble           : 1
+  BranchPredictor          : 0
+  DbgTriggerEn             : 0
+  SecureIbex               : 0
+  PMPEnable                : 0
+  PMPGranularity           : 0
+  PMPNumRegions            : 4
+  MHPMCounterNum           : 0
+  MHPMCounterWidth         : 40

ibex_core.core

@@ -36,6 +36,10 @@ filesets:
       - rtl/ibex_wb_stage.sv
       - rtl/ibex_dummy_instr.sv
       - rtl/ibex_core.sv
+      - rtl/isolde_fetch2exec_if.sv
+      - rtl/isolde_fetch_vleninstr.sv
+      - rtl/isolde_decoder.sv
+      - rtl/isolde_exec_block.sv
       - rtl/ibex_pmp_reset_default.svh: {is_include_file: true}
     file_type: systemVerilogSource
 

ibex_pkg.core

@@ -9,6 +9,8 @@ filesets:
   files_rtl:
     files:
       - rtl/ibex_pkg.sv
+      - rtl/isolde_register_file_pkg.sv
+      - rtl/isolde_decoder_pkg.sv
     file_type: systemVerilogSource
 
 targets:

ibex_top.core

@@ -19,6 +19,9 @@ filesets:
       - lowrisc:prim:onehot_check
       - lowrisc:prim:onehot
     files:
+      - rtl/isolde_x_register_file_if.sv
+      - rtl/isolde_register_file_if.sv
+      - rtl/isolde_register_file_ff.sv
       - rtl/ibex_register_file_ff.sv # generic FF-based
       - rtl/ibex_register_file_fpga.sv # FPGA
       - rtl/ibex_register_file_latch.sv # ASIC