[Bug] Package parsing misses dependencies when use clause is not used

[SzymonHitachi]

Assume having a package in a file pkg_a.vhd:

package pkg_a is

    type my_type_t is (A, B, C)

end package pkg_a;

and a second package pkg_b in a file pkg_b.vhd which scopes an object from pkg_a

package pkg_b is

    alias mytype is work.pkg_a.mytype;

end package pkg_b;

When used in above way VUnit doesn't detect dependency between pkg_b.vhd and pkg_a.vhd even though this is a valid use case in VHDL. The outcome will be that the pkg_b won't compile due to pkg_a not being compiled yet due to wrong compilation order.

However if type is imported directly through use clause, the dependency is detected.

-- any of the below works
use work.pkg_a.all;
use work.pkg_a.mytype;

package pkg_b is

    -- direct designation is ofcourse now not needed since the type is imported already by `use` clause
    alias mytype is work.pkg_a.mytype;

end package pkg_b;

[LarsAsplund]

Yes, there are legal VHDL/SV constructs that VUnit can't detect. Our ambition has not been to create a complete parser as that would increase the analysis time and it would also be a major effort considering that HDLs are hard to parse. Our aim is to have a parser that covers the more common cases which leaves you with two options. Either write your VHDL in a "VUnit friendly" way (as you suggested) or use add_dependency_on if you're not in control of how the RTL is written.

I also see a future where we could make use of an external open source parser that fits our purposes. A dedicated parser project may give us a more complete parser without sacrificing performance.