New issue

Have a question about this project? Sign up for a free GitHub account to open an issue and contact its maintainers and the community.

Sign up for GitHub

By clicking “Sign up for GitHub”, you agree to our terms of service and privacy statement. We’ll occasionally send you account related emails.

Already on GitHub? Sign in to your account

Jump to bottom

Adapt Verilog generator to use assign statements #125

Open

atomb opened this issue May 21, 2021 · 0 comments

Labels

atomb commented May 21, 2021

The current Verilog generation backend produces Verilog like the following:

output [31:0] out = wr_5;

According to @rtadros125, this isn't considered good form. Instead, we should do something like:

output [31:0] out;
assign out = wr_5;

ABC seems to accept the latter form, so we should probably modify the generator to produce it.

The text was updated successfully, but these errors were encountered:

robdockins added the enhancement label

Sign up for free to join this conversation on GitHub. Already have an account? Sign in to comment